1. Field of the Invention
The present invention relates to an electric circuit and a semiconductor package capable of eliminating source noise in a semiconductor integrated circuit which performs high-speed operation.
2. Description of the Related Art
The current used in a semiconductor integrated circuit tends to increase by many times as the bus width of a semiconductor system increases from 8 bits to 16 bits, from 16 bits to 32 bits, and from 32 bits to 64 bits. Also, as the speed of the semiconductor system increases, the current change interval is shortened by several times, from 10 nsec. to several nsec. and to less than 1 nsec. As a result, recently, the change rate of the current consumed by a semiconductor device (dI/dt) has increased by several tens of times. With such an increasing current change rate, source noise tends to increase.
When an inductance exists between a ground terminal of a power supply for a semiconductor device and the power supply, voltage variation is generated in proportion to current change. This develops to source noise and becomes a cause of malfunction of the semiconductor device. In order to prevent this problem, a bypass capacitor is conventionally provided near power supply/ground terminals of a semiconductor device. This reduces the source impedance as observed from the semiconductor device and thus reduces source noise. However, in a construction where a plurality of semiconductor devices and bypass capacitors are arranged, a current flows from one semiconductor device, not only to the corresponding bypass capacitor near the semiconductor device, but also to another bypass capacitor.
FIG. 28 shows a circuit diagram showing a current flowing to a semiconductor circuit.
Referring to FIG. 28, the reference numerals 35a and 35b denote semiconductor devices, 36 denotes an output terminal, 37a and 37b denote bypass capacitors, 38 denotes a signal line, 39 denotes a normal current flowing to the semiconductor device 35a, and 40 denotes an undesirable current which may cause a variation in source potential. The current 40 generates source noise for the other semiconductor device 35b and becomes a cause of electromagnetic radiation from power supply/ground planes.
In order to reduce the above phenomena, TECHNICAL REPORT OF IEICE, EMCJ97-82, for example, describes a method which uses a substrate capable of reliably decoupling adjacent semiconductor devices mounted thereon from each other. FIG. 29 illustrates this method.
Referring to FIG. 29, the reference numeral 35 denotes semiconductor devices, 36 denotes an output terminal, 37 denotes bypass capacitors, 38 denotes a signal line, 41 denotes decoupling coils, 42 denotes a power supply plane, and 43 denotes a ground plane.
The decoupling coil 41 is inserted between the power supply terminal of each semiconductor device 35 and the power supply plane 42. One terminal of the bypass capacitor 37 is connected with the power supply terminal of the semiconductor device 35, and the other terminal thereof is grounded. In this way, a high-frequency current flowing to the semiconductor device 35 is supplied from the bypass capacitor 37 disposed near the semiconductor device 35 without flowing to the power supply plane 42.
The reason for the above is that, by the insertion of the decoupling coil 41, an impedance Zc=1/(j.omega.C) on the side of the bypass capacitor 37 as observed from the semiconductor device 35 becomes lower than an impedance Ze=j.omega.L on the side of the power supply as observed from the semiconductor device 35.
The larger the ratio of the impedance Ze on the side of the power supply as observed from the semiconductor device 35 to the impedance Zc on the side of the bypass capacitor 37 as observed from the semiconductor device 35 is, the greater the effects of attenuating source noise for other semiconductor devices and electromagnetic radiation from the power supply/ground planes are.
With the above conventional construction, however, if the decoupling coil 41 is large, the impedance also increases at a low frequency, resulting in failure to supply a current required for the semiconductor device 35 from the power supply. In order to avoid this problem, it is required that the decoupling coil 41 be sufficiently small and that the bypass capacitor 37 be sufficiently close to the semiconductor device 35 for reducing parasitic inductance.
If the decoupling coil 41 and the bypass capacitor 37 are constructed as discrete elements, there arise problems such that elements with appropriate values are not obtainable and that the impedance Zc cannot be sufficiently made small due to parasitic inductance possessed by the bypass capacitor 37. As a result, sufficient effects of attenuating source noise and electromagnetic radiation from the power supply/ground planes are not obtained.
Construction of discrete elements has other disadvantages as follows. The cost increases. The area required for implementation of these elements increases and thus reduction in size of the resultant device becomes difficult. With an increased size of the device, high-speed operation is not possible.
In a high-speed operating circuit, in general, each of the ground plane 43 and the power supply plane 42 is formed as an entire pattern on an inner layer of the substrate. The signal line 38 is formed so as to constitute a micro-strip line structure with the ground plane 43 formed on the first inner layer nearest to the signal line 38 among underlying inner layers of the substrate. Alternatively, the signal line 38 is formed so as to constitute a micro-strip line structure with the power supply plane 42 formed on the first inner layer among the underlying inner layers of the substrate as described above.
Herein, the former construction may also be referred to as the construction having the ground plane 43 right under the signal line 38, whereas the latter construction may also be referred to as the construction having the power supply plane 42 right under the signal line 38.
However, when the signal line 38 constitutes a micro-strip line structure with the power supply plane 42 in the construction shown in FIG. 29, the power supply plane 42 exists right under the signal line 38. In this case, a feedback current of a current flowing to the output terminal 36 flows to the power supply plane 42 via the decoupling coil 41. This increases the impedance and thus high-speed operation is not possible. For this reason, the construction shown in FIG. 29 can be fabricated only on a surface of a substrate right under which the ground plane 43 exists, but not on a surface thereof right under which the power supply plane 42 exists.
As a result, in a high-speed operating circuit, implementation may be limited, or a longer interconnection route may be required for implementation. Otherwise, implementation itself may be impossible. Further, for these reasons, the following disadvantages arise. The cost increases. The area required for implementation increases and thus reduction in size of the resultant device becomes difficult. With an increased size of the device, high-speed operation is not possible.
As described above, the conventional semiconductor integrated circuit aims at reducing source noise and electromagnetic radiation by decoupling semiconductor circuits from each other with respect to high frequency using decoupling coils. However, the semiconductor integrated circuit has problems such that implementation is limited, the cost increases, the source impedance increases due to increase of an impedance component, the area for implementation increases, and high-speed operation becomes difficult.